1. Field of the Invention
This invention relates to multi-bit-per-cell memories and to data arrangements in multi-bit-per-cell memories that minimize the effect of memory errors and defects.
2. Description of Related Art
Recent developments in multi-media applications such as digital music in MP3 and AC3 formats, digital imaging for digital cameras, digital video for DV and digital camcorders, and the popularity of the internet and wireless communications have resulted in an explosive demand for cost-effective mass data storage devices with ultra high-density. Multi-bit-per-cell memories can effectively fill these needs. Multi-bit-per-cell memories use storage and retrieval techniques that provide N bits of data per memory cell and thereby increase the amount of data stored in a memory array by a factor of N when compared to binary memories. Multi-bit-per-cell Flash memories, in particular, are especially suitable for portable and battery-powered multi-media applications because Flash memories are non-volatile and provide a high-density of memory cells in an integrated circuit.
A concern when using multi-bit-per-cell memories is the accuracy of the storage and retrieval techniques. In particular, when a threshold voltage of a floating gate transistor in a memory cell represents an N-bit data value, a small error in the determination or the setting of the threshold voltage can cause a data error. Alpha particles, if not addressed properly, can also more easily create soft errors in multi-bit-per-cell memories than in conventional binary memories. Fortunately, many multi-media applications are error-tolerant or have built-in error detection and correction schemes for critical data such as the header information in an MP3 music data stream. Thus, a small number of data errors or defective memory cells may not cause a noticeable change in output quality. However, a large number of errors or multiple consecutive error bits may result in significant degradation in quality if these errors exceed the limits of the error correction technology.
Another concern is memory defects. Redundant or spare memory cells or arrays improve manufacturing yields of high-density memory ICs, particularly multi-level memories. Repair operations during fabrication of the memory ICs activate redundant memory cells of arrays in response to a test detecting one or more defective memory cells. Accordingly, before the IC memory device leaves the factory, test and repair operations can replace defective memory cells that have gross or hard defects with working redundant memory cells. Other memory cells may pass the initial testing but later fail or degrade quickly during the lifetime of the IC memory. For example, non-volatile memory cells containing floating gate transistors could have threshold voltages that change due to charge gain, charge loss, or contamination. Memory cells can also become sensitive to operating parameters such as supply voltage, temperature, and the data pattern, or endurance-related effects. The possibility of these xe2x80x9clatentxe2x80x9d defective memory cells often limits the use of multi-bit-per-cell memories and the maximum number of bits stored per cell because multi-bit-per-cell memories are more susceptible to latent defects.
FIG. 1 conceptually illustrates operation of a multi-bit-per-cell memory when recording an input serial data stream and playing back the serial data stream as output data. The data streams define input and output bit sequences 110 and 150. The conventional multi-bit-per-cell storage scheme groups N adjacent bits from bit sequence 110 into an N-bit value. An N-to-1 translator 120 converts the N-bit value into one of the 2N levels (e.g., a corresponding threshold voltage level) that can be written into a single memory cell 130-1 of a memory array 130. (In FIG. 1, N is four, and each translator 120 converters a 4-bit value into one of 16 levels for storage in a memory cell.) The next N data bits from the serial data bit stream are grouped and written into a physically adjacent memory cell 130-2, typically in the same row or column as the previously accessed memory cell.
During the read (or playback) operation, the level stored in each memory cell is read, and a 1-to-N translator converts the read level back into the N adjacent bits. Finally, assembly of all of the bits read from adjacent memory cells constructs the bit sequence 150.
A multi-level memory having two translators 120 and 140 for each memory cell has too much overhead to be practical. FIG. 2 illustrates a more typical multi-bit-per-cell memory 200 including a memory array 210 with one N-to-1 translator 220 and one 1-to-N translator 230 that are multiplexed or shared among all the memory cells. A multi-level write circuit 225 programs a memory cell in array 210 according to the level from N-to-1 translator 220, and a multi-level read circuit 235 reads a memory cell to provide a read level to 1-to-N translator 230. A shift register 250 and a multiplexing circuit 240 control partitioning of an input serial data stream of M-bits into N-bit data units for N-to-1 translator 220 and assembling of N-bit data units from 1-to-N translator 230 to form the output serial data stream.
In the conventional scheme, any single memory cell failure can potentially affect N adjacent bits of the serial data stream. In particular, a slight shift in the read or written threshold voltage of a memory cell can corrupt all N adjacent data bits stored in the memory cell. For example, conventional binary coding of threshold voltage levels has adjacent data values 011 . . . 11b and 100 . . . 00b correspond to adjacent threshold voltage levels. A shift from one threshold voltage level to the adjacent threshold voltage level can changes all N bits (e.g., from 011 . . . 11b to 100 . . . 00b). If these N adjacent data bits all come from the same audio sample or the same pixel in an image, the error may cause a significant and noticeable distortion in the output signal (audio or image) upon playback.
U.S. Pat. No. 5,909,449, entitled xe2x80x9cMulti-Bit-Per-Cell Non-Volatile Memory with Error Detection and Correction,xe2x80x9d which is hereby incorporated by reference in its entirety, describes Gray coding of threshold voltages to prevent more than a single bit error when a memory cell threshold voltage shifts from one level to an adjacent level. The Gray coding method is subject to multiple consecutive bit errors if a single memory cell fails in a more significant way than a single level shift. Accordingly, further methods for minimizing the effects of data errors in multi-level memories are sought.
In accordance with an aspect of the invention, a data management method minimizes the effect that defective memory cells have on the quality of the data stored in multi-bit-per-cell memories.
A data management method in accordance with one embodiment of the invention mixes or scrambles a bit sequence from an input serial data stream before storage. The mixing or scrambling separates consecutive bits from each other. Consecutive bits are stored in different multi-level memory cells that are preferably physically spaced apart from each other in a memory array. Accordingly, any single memory cell failure or adjacent memory cell failures (such as one or more cells along a column or along a row) caused by threshold voltage drift, localized defects, endurance-related failures or soft errors, does not cause a long string of consecutive bit errors. The mixing of data bits spreads the effect of any single memory cell failure among data coming from, for example, different audio samples (at different times or different frequencies) or different pixels (for image or video) and typically makes the defects much less noticeable or easier to correct.
One embodiment of the invention is a multi-bit-per-cell memory that includes a storage array, a scrambler, and a write circuit. Each memory cell in the storage array stores N bits of information. The scrambler receives data including a group of M data bits and generates a set of scrambled N-bit values from the group of M data bits. Each scrambled N-bit value has bits in an order that differs from the bit order in the group. The write circuit receives the set of scrambled N-bit values from the scrambler and writes each scrambled N-bit value in an associated memory cell. In one embodiment, the memory further includes: a read circuit and a descrambler, but the descrambler can be implemented using the elements of the scrambler. The descrambler receives a set of N-bit values read from associated memory cells of the storage array and mixes bits from the N-bit values to reconstruct a group of M data bits.
Exemplary implementations of the scrambler include: a data input port hardwired to scramble data bits that are output from an output port; a linear buffer that outputs data bits in an order that differs from the order in which data was stored; and a buffer array with an address control circuit operable in a first mode that increments a row address for each bit accessed in the buffer array and a second mode that increments a column address for each bit accessed in the buffer array. With the buffer array, the scrambler provides a scrambled N-bit value by: sequentially writing bits from the group into the buffer array while operating in one of the first and second modes; changing mode; and reading N bits from the buffer array. For reading and data output, the scrambler provides output data by: sequentially writing bits from the read circuit into the buffer array while operating in one of the first and second modes; changing mode; and reading the output data from the buffer array.
In accordance with another embodiment of the invention, a method for writing or arranging data in a multi-bit-per-cell memory, includes scrambling data bits from an input serial data stream to create a scrambled data stream; partitioning the scrambled data stream into a set of N-bit values; and writing each N-bit value in a corresponding memory cell. Consecutive bits from the input serial data stream are not consecutive in the scrambled data stream so that a data error or defect in a single memory cell does not cause a string of N consecutive data errors. Operating the memory further includes reading a set of N-bit values from a set of the memory cells, and mixing bits from different N-bit values to generate output data. Circuitry inside an integrated circuit memory device such as the multi-bit-per-cell memories described herein can perform the scrambling, partitioning, writing, reading, and mixing.